Showing posts with label Circuit Simulation. Show all posts
Showing posts with label Circuit Simulation. Show all posts

Sunday, August 27, 2017

Electronics Tutorial: Diode Connected JFET for Overvoltage Protection Applications


If you need to protect sensitive circuits from overvoltage breakdown conditions, diodes are one way. When the input voltage becomes to high, the diode will conduct and limit the voltage to around 0.7 volt. However, if your circuit is used to measure low-level currents, even a slightly biased diode can siphon off a significant amount of current - seriously degrading measurement accuracy

In order to keep your measurements accurate and protect your measurement circuitry you will need a diode that has a very low current in the non conduction region (below the forward bias voltage). In this case, a JFET connected diode is an alternative. When a JFET is connected as a diode, it exhibits very low levels of leakage current in the non-conduction region.

A JFET connected diode is simple to build. Just connect the source and the drain of an N-Channel JFET together. The gate of the JFET will serve as the cathode and the drain/source will be the anode. Such a connection is shown in the LTSpice schematic below. For this circuit, a 1 Volt sine wave (at 300 Hz) is applied to the JFET diode.

A diode can be easily constructed with an N-Channel JFET

The output of the JFET diode is taken across the load resistor, R1, Just like a regular diode, it will clip the negative portion of a sine wave. Also just like a regular diode, it will not conduct until the driving voltage reaches 0.7 volt. This shortens the duty cycle of the output waveform and lowers the peak voltage of the output waveform. 


The JFET diode clips the negative cycle of a sine wave

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Diode Connected JFET Protects Op Amps
Common Circuit Applications (JFET Diode)

Electronics Tutorial: JFET Current Voltage Characteristics: IV Curves with LTSpice


LTSpice offers one way to generate IV curves without an expensive curve tracer. However, how well LTSpice IV curves match the actual device’s IV curves depends on how accurately the JFET model matches the actual device. Not all LTSpice models are created equal. Some models are bare bones and will only give you a a rough estimate of the actual IV curves.  Most models include the pinchoff voltage and beta parameter, which take into account the drain to source saturation current. Additionally, most models are only specified for a given set of process conditions. This process condition most often corresponds to the minimum data specifications on the data sheet.

JFET  IV Characteristics (Curve Tracing)

The basic circuit for generating IV curves for a N channel is shown below. It utilizes two supplies,  one for generating the gate to source voltage (VGS) and one for generating the drain to source voltage (VDS). During the simulation, the gate to source voltage is kept constant and the drain to source voltage is stepped from 0 Volts to a maximum drain to source voltage. 

However, a complete set of IV curves requires that the drain-to-source current be measured at different VGS voltages.  The typical LTSpice simulation command for generating  a set of  JFET IV  curves is

.DC VDS 0  15 0.01 VGS -1.5 0 -0.3




LTSPICE Circuit Schematic for Generating IV Curves for a JFET


Th e DC sweep command instructs the simulator to first set the gate voltage to -1.5 volts and then sweep the VDS power supply from 0 to 15 volts in 0.01 volt steps. Once that sweep is complete, the VGS supply is incremented by -0.5 Volts to  -1.5 Volts and VDS is swept again from 0 to 15 volts  This process continues until VGS reaches 0 V. A N-Channel JFET is fully on when the gate-to-source voltage is 0 V. When VGS is at the pinchoff voltage the drain to source current is zero. For the default JFET LTSPICE model used in this example, the pinchoff parameter is at its default value of - 2 Volts.



IV Characteristics of Default N-Channel JFET LTSPICE Model


The default N-Channel default model also uses LAMBA = 0.  Because LAMBDA is zero, the slope of the IV curves in the saturation region is zero also.  For the most part, this is not the way a real JFET operates. The IV curves in the saturation region have a small slope, which is set with the value of LAMBDA. 

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